发明名称 COMMUNICATION MEDIATION DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a communication mediation device reduced in power consumption during idling. <P>SOLUTION: An internal clock generation circuit 15 starts generation of clock CLK 1 with frequency of 480 MHz in response to detection of arrival of a second packet at a time interval shorter than 125μs that is a first interval by a HS idle detection circuit 10, supplies the clock to a HSDLL (high speed delay line phase locked loop) 16, an elasticity buffer 17, an Rx data deserializer 18, and a Tx data serializer 12, and stops generation of the clock CLK 1 with frequency of 480 MHz in response to detection that the time interval of arrival of the first packet is returned to 125μs. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008171242(A) 申请公布日期 2008.07.24
申请号 JP20070004484 申请日期 2007.01.12
申请人 KAWASAKI MICROELECTRONICS KK 发明人 NAKANO HIDEYO
分类号 G06F1/04;H03K5/19;H04L25/02 主分类号 G06F1/04
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