发明名称 MANUFACTURING METHOD OF SILICON EPITAXIAL WAFER
摘要 PROBLEM TO BE SOLVED: To provide a method of manufacturing, with high productivity, an epitaxial wafer of parallel pn junction structure in high quality, by evenly removing a rise in a silicon in forming a parallel pn junction structure for precise and efficient final polishing process of a silicon substrate surface. SOLUTION: The manufacturing method of the epitaxial wafer includes a process in which an oxidized film having a trench formation pattern is formed on the surface of a silicon substrate of first conductive type, a process in which a trench is formed with the oxidized film as a mask, a process in which a region of second conductive type is formed in the trench by a selective epitaxial growth method, a process in which a rise in the silicon that is generated in the opening of the trench at the epitaxial growth is etched by spin-etching for flattening, a process for removing the oxidized film, and a process in which the main surface of the silicon substrate subjected to parallel pn junction formation is polished for flattening after the oxidized film is removed. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008171972(A) 申请公布日期 2008.07.24
申请号 JP20070003070 申请日期 2007.01.11
申请人 SHIN ETSU HANDOTAI CO LTD 发明人 TAKAMIZAWA SHOICHI
分类号 H01L29/78;H01L21/205;H01L21/304;H01L21/306;H01L21/336;H01L29/06;H01L29/739 主分类号 H01L29/78
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