| 摘要 |
<p>A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C1 during the first period T1 of the clock signal MCLK based on a current based on an audio signal eS, changes the voltage of the first integration circuit C1 based on a constant bias current in the opposite direction while changing the voltage of a second integration circuit C2 during the second period T2, and changes the voltage of the second integration circuit C2 based on the bias current during the third period T3. The amount of time from the start of the second period T2 until the voltage of the first integration circuit C1 reaches the reference voltage Vth is detected, and the amount of time from the start of the third period T3 until the voltage of the second integration circuit C2 reaches the reference voltage Vth is detected. The voltage of the first integration circuit C1 is kept at the reference voltage Vth from when the voltage of the first integration circuit C1 reaches the reference voltage Vth until the start of the third period T3, and the voltage of the second integration circuit C2 is kept at the reference voltage Vth from when the voltage of the second integration circuit C2 reaches the reference voltage Vth until the start of the fourth period T4. A pulse signal is generated, in which the pulse widths are equal to the amounts of time required for first and second integration circuits C1 and C2 to reach the reference voltage Vth.</p> |
