MICROSTRIP SPACER FOR STACKED CHIP SCALE PACKAGES, METHODS OF MAKING SAME, METHODS OF OPERATING SAME, AND SYSTEMS CONTAINING SAME

摘要

A chip package includes a microstrip spacer disposed between a first die and a second die. The microstrip spacer includes electrically conductive planes that are ground planes for at least one of the first die and the second die. A method includes operating the first die at a first clock speed and operating the second die at a second clock speed. A system includes a chip package with a microstrip spacer and a system housing.