| 摘要 |
An EPROM cell (70) includes a semiconductor substrate (52), having source and drain regions (76, 74), a floating gate (72), including a semiconductive polysilicon layer (56) electrically interconnected with a first metal layer (60), and a control gate (64), including a second metal layer. The floating gate (72) is disposed adjacent to the source (76) and drain (74) regions and separated from the semiconductor substrate (52) by a first dielectric layer (54), and the second metal layer (64) of the control gate is capacitively coupled to the first metal layer (60) with a second dielectric layer (62) therebetween. |
