| 摘要 |
According to one exemplary embodiment, a method includes forming first, second, and third shallow trench isolation regions in a substrate, wherein the second shallow trench isolation region is situated between the first and the third shallow trench isolation regions. The second shallow trench isolation region is removed to form a transistor channel trench. A substantially U-shaped gate is formed in the transistor channel trench. According to another embodiment, a transistor includes a substrate, and first and second shallow trench isolation regions in the substrate. A substantially U-shaped gate is formed in the substrate between said first and second shallow trench isolation regions.
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