| 摘要 |
A semiconductor memory device capable of adjusting on die termination(ODT) operation timing efficiently is provided to find an error due to ODT operation easily even when the ODT operation has different characteristics from the design by external conditions like fabrication process. A latency control part(120,220) generates an ODT(On Die Termination) operation enable signal by delaying an ODT operation signal inputted from the outside during expected latency. A control signal generation part generates a control signal to control waveform change of the ODT operation enable signal. A trimming control part(130,230) changes the waveform of the ODT operation enable signal in response to the control signal. A termination circuit connects a termination resistor to an impedance control node in response to the ODT operation enable signal outputted from the trimming control part.
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