Scan path circuit and semiconductor integrated circuit comprising the scan path circuit

摘要

Each of D flip-flops (FFs) 13 a to 13 f constituting a scan path circuit has a normal operation input circuit to be selected in a normal operation and a test operation input circuit to be selected in a test operation, and a control signal having an intermediate voltage between a supply voltage and a ground voltage is sent from a voltage generating circuit 17 to the test operation input circuit of each FF in the test operation. In this case, the amount of an output change in data in each FF is smoother than that in the case in which the supply voltage is applied. Consequently, the delay time of the data is increased. The intermediate voltage to be applied to each FF in the test operation is determined based on a feedback signal sent from a test circuit 15 for checking whether scanned-out data have an error or not.