| 摘要 |
<p>A wafer burn-in test circuit is provided to apply dynamic stress in a wafer burn-in mode and to screen an initial defect of a semiconductor memory device effectively by using an address toggle signal generation method. An address toggle signal generation unit(200) generates an address toggle signal in response to an address signal of a constant period. A reset signal generation unit(300) receives a wafer burn-in mode activation signal, the address signal, and a reset decision signal. A refresh test mode signal generation unit(400) receives the address toggle signal and the reset signal and generates a refresh test mode signal. A refresh period signal generation unit(100) receives the address toggle signal and the refresh test mode signal and generates a refresh period signal.</p> |
