DELAY LOCKED LOOP CIRCUIT CAPABLE OF TESTING A REPLICA PATH, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE DELAY LOCKED LOOP CIRCUIT, AND METHOD OF TESTING A REPLICA PATH OF DELAY LOCKED LOOP CIRCUIT

摘要

A delay locked loop circuit capable of testing a replica path, a semiconductor memory device including the delay locked loop, and a method for testing the replica path of the delay locked loop are provided to test the characteristics of a normal path itself under the condition of not operating the delay locked loop circuit and then to test the characteristics of the replica path itself using the characteristics of the normal path. According to a delay locked loop circuit(105), a test clock transmission part(110) outputs an external clock signal as a normal path test clock signal or a replica path test clock signal, in response to a replica path test mode signal indicating a test mode included in a DLL off mode where the delay locked loop circuit is disabled. The replica path test mode signal is enabled in the replica path. A replica path(125) outputs an output replica clock signal by delaying the replica path test clock signal as much as delay time of circuits included in a normal path(130). In the replica path test mode, the normal path outputs internal output data outputted from a memory cell of a semiconductor memory device including the delay locked loop circuit in response to the output replica clock signal. In a normal path test mode where the replica path test mode signal is disabled, the normal path outputs internal output data outputted from the memory cell in response to the normal path test clock signal.