发明名称 Non-planer mos structure with a strained channel region
摘要 An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.
申请公布号 GB2437867(B) 申请公布日期 2008.07.09
申请号 GB20070014637 申请日期 2006.01.04
申请人 INTEL CORPORATION 发明人 BRIAN DOYLE;SUMAN DATTA;BEEN-YIH JIN;ROBERT CHAU
分类号 H01L29/786;H01L21/336 主分类号 H01L29/786
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