| 摘要 |
The present invention is concerned with a phase comparator circuit and provides an erroneous phase lock detection circuit that detects erroneous phase lock occurring when the duty cycle of data deviates from 100% in a comparison of a phase difference between the data and a clock. The erroneous phase lock detection circuit incorporated in a phase comparator that detects a phase difference between data and a clock comprises: a first phase detection unit that detects a phase difference by measuring a difference between the leading edge of the data and the phase of the clock and transmits an average of phase differences; a second phase detection unit that detects a phase difference by measuring a difference between the trailing edge of the data and the phase of the clock and transmits an average of phase differences; and an erroneous phase lock verification unit that, when the difference between the average phase difference sent from the first phase detection unit and the average phase difference sent from the second phase detection unit exceeds a predetermined range, verifies erroneous phase lock.
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