| 摘要 |
A clock generator in a semiconductor memory device is provided to generate an internal clock toggling at timing according to the specification of the semiconductor memory device regardless of setup time according to a clock enable signal. A second clock enable signal output unit outputs a second clock enable signal by buffering and delaying a first clock enable signal. A clock synchronization enable signal output unit outputs a clock synchronization enable signal by synchronizing the second clock enable signal with a clock enable latch signal. A clock enable buffer signal generation unit generates a clock enable buffer signal disabled in response to the enable of the clock synchronization enable signal and enabled in response to the enable of the second clock enable signal. A second external clock output unit outputs a second external clock by buffering a first external clock in response to the clock enable buffer signal. A third external clock output unit outputs a third external clock by delaying the second external clock. A control unit controls output timing of the clock enable latch signal and an internal clock, by receiving the clock synchronization enable signal, the clock enable buffer signal, the second external clock and the third external clock. The control unit includes a first signal output unit(62), a second signal output unit(64), a latch signal output unit(66B) and an internal clock output unit(68). The first signal output unit outputs a first signal, and the second signal output unit outputs a second signal. The latch signal output unit outputs the clock enable latch signal. The internal clock output unit outputs the third external clock as the internal clock in response to the clock synchronization enable signal.
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