发明名称 |
Clock jitter minimization in a continuous time sigma delta analog-to-digital converter |
摘要 |
A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.
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申请公布号 |
US7397291(B1) |
申请公布日期 |
2008.07.08 |
申请号 |
US20070621844 |
申请日期 |
2007.01.10 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
PARKES, JR. JOHN J.;MITTEL JAMES G.;RICHES JAMES J. |
分类号 |
H03K3/70;H03K3/023;H03M1/66 |
主分类号 |
H03K3/70 |
代理机构 |
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地址 |
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