发明名称 |
Auto-gain controlled digital phase-locked loop and method thereof |
摘要 |
A digital PLL system includes a first multiplier coupled to a phase difference signal for multiplying the phase difference signal by a first gain factor; a second multiplier coupled to the phase difference signal for multiplying the phase difference signal by a second gain factor; a digital loop filter coupled to the first multiplier and the second multiplier for providing an integral signal and a proportional signal and for generating a control signal according to the integral signal and the proportional signal; and an auto-gain control (AGC) unit coupled to the first multiplier, the second multiplier, and the digital loop filter. The AGC unit further comprises a first control unit for updating the first gain factor according to the integral signal; and a second control unit for updating the second gain factor according to the proportional signal.
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申请公布号 |
US7397313(B2) |
申请公布日期 |
2008.07.08 |
申请号 |
US20070675068 |
申请日期 |
2007.02.14 |
申请人 |
MEDIATEK INC. |
发明人 |
WANG PING-YING;YANG MENG-TA |
分类号 |
H03L7/085;G11B5/09;H03L7/093 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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