| 摘要 |
A semiconductor and a method for manufacturing the same are provided to minimize the influence between adjacent devices by securing a sufficient margin between adjacent capacitors. Each cell of a memory cell array includes an active region(302), a gate, a storing electrode(312), a storing electrode contact plug, and a source/drain region. The active region is defined by an isolation structure located in a semiconductor substrate. The gate is located on a gate region(304) passing a predetermined part of the active region. The storing electrode is located on an upper portion of the active region at a side of the gate. The storing electrode contact plug is formed between the storing electrode and the active region on a lower portion thereof. The storing electrode contact plug electrically connects the active region to the storing electrode. The storing electrode contact plug is overlapped with the storing electrode. The source/drain electrode is located on the active region at both sides of the gate.
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