Wafer level chip scale package having pillar in solder bump

摘要

PURPOSE: A wafer level chip scale package having pillar in a solder bump is provided to prevent the package from being inclined and control the height of the solder bump. CONSTITUTION: A wafer level chip scale package is provided with a package body structure(100) including a realignment connecting line pattern(115) and an insulating layer(110) formed on the upper portion of the realignment connecting line pattern(115) for exposing the predetermined portion of the realignment connecting line pattern, a pillar(120) formed on the exposed realignment connecting line pattern, and a pillar built-in solder bump(140) for contact the exposed realignment connecting line pattern. Preferably, a chip scale package or a wafer level package is used as the package body structure.