发明名称 LATCH CIRCUIT AND DESERIALIZER CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To increase the maximum operating frequency of a latch, and to decrease power consumption. <P>SOLUTION: The latch has: a precharge section 110; a storage logic section 120; an input amplification section 130; and a clock synchronous switch 140. In this case, the storage logic section 120 and the input amplification section 130 are arranged in the same transistor hierarchy, thus forming the entire transistor hierarchy in three hierarchies. A current source 150 is connected to the storage logic section 120 for allowing the current source 150 to control current passing through the storage logic section 120. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008153983(A) 申请公布日期 2008.07.03
申请号 JP20060340300 申请日期 2006.12.18
申请人 FUJITSU LTD 发明人 CHO SHISEI
分类号 H03K3/356;H03K3/0233;H03K17/00 主分类号 H03K3/356
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