| 摘要 |
PROBLEM TO BE SOLVED: To reduce the circuit area of a semiconductor device to be designed. SOLUTION: A circuit simulation device 10 includes: a delay time verifying part 252 for calculating a delay time T<SB>d</SB>under a prescribed environmental condition concerning static timing verification with respect to a logical circuit 100 after layout, and performing hold verification; and a layout correcting part 253. When hold violation is determined in the hold verification, the delay time verifying part 252 selects a correcting method corresponding to the environmental condition from the plurality of layout correcting methods. The layout correcting part 253 corrects the layout of the logical circuit with the use of the correcting method selected by the delay time verifying part. COPYRIGHT: (C)2008,JPO&INPIT
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