| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a receiving error when a Ser/Des circuit transits from a dormancy state to a power-up state. <P>SOLUTION: If a receiver 21 transits from the dormancy state P1 to the power-up state P0, a reset control circuit 21m starts to count a system clock obtained from PLL31 by a delay circuit 21m-1. Then, the reset control circuit 21m cancels resets of a digital filter 21e and a PI control circuit 21f after the delay circuit 21m-1 counts X cycles. <P>COPYRIGHT: (C)2008,JPO&INPIT |
