发明名称 Method of verifying line reliability and method of manufacturing semiconductor device
摘要 Provided are a method of verifying line reliability and a method of fabricating a semiconductor substrate to improve the line reliability. The semiconductor device fabricating method includes: forming an interlayer insulating layer having a via hole on a semiconductor substrate; forming a seed layer on the interlayer insulating layer; performing an ammonia plasma process on the seed layer to reduce the surface of the seed layer; and forming a copper line using the surface roughness reduced seed layer.
申请公布号 US2008160655(A1) 申请公布日期 2008.07.03
申请号 US20070930278 申请日期 2007.10.31
申请人 HONG JI HO 发明人 HONG JI HO
分类号 H01L21/66;H01L21/4763 主分类号 H01L21/66
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