发明名称 CIRCUIT FOR CALCULATING TEXTURE PATTERN SIZE
摘要 PROBLEM TO BE SOLVED: To allow accurate texture mapping even on a polygon outline. SOLUTION: This circuit interpolates linearly a geometric coordinate value defined on a polygon apex, a texture mapping address and the like. The circuit outputs crossing information of the outline and a pixel to an FIFO memory. The circuit reads out outline information, when receiving the outline information to be compared with an x-axis coordinate value and when a point under interpolation is one on the outline, to find an x-axial coordinate value or a y-axial coordinate value, a texture mapping coordinate value and a perspective transformation relation value, in a point where the outline is crossed with a grid. Distances between the x- and y-coordinate values and between the texture coordinate values are calculated using not grid crossing information but adjacent pixel information, even on the outline, and further a polygon magnification and a texture ratio are found by dividing those distances, respectively. A texture RAM address generator receives calculation results therein to select the optimum pattern. Brightness in an interpolation point is determined based on the texture information and the like. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008152743(A) 申请公布日期 2008.07.03
申请号 JP20060357294 申请日期 2006.12.18
申请人 KAADEIKKU CORPORATION:KK 发明人 IKEDO TSUNEO
分类号 G06T15/04 主分类号 G06T15/04
代理机构 代理人
主权项
地址