| 摘要 |
A level shifter circuit 28 has a first buffer circuit 30 and a second buffer circuit 32, 34 . An intermediate signal generated by the first buffer circuit 30 is directly passed to the second buffer circuit 32, 34 to control output of one of its output signal levels. A feedback signal generated in response to the input signal within the first power domain containing the first buffer circuit 30 is passed directly to the second buffer circuit 32, 34 to control the output signal level reaching the other of the output values. A feedback circuit comprising cross-coupled PMOS transistors 38, 40 is provided to boost the feedback signal level up to the voltage level of the second voltage domain which contains the feedback circuit 38, 40 as well as the second buffer circuit 32, 34 . The level shifter circuit 28 has a low latency and a low static power consumption.
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