ASYMMETRIC RISE/FALL TIME AND DUTY CYCLE CONTROL CIRCUIT
摘要
Modules and signal control circuits configured to at least partially compensate for or adjust for asymmetric rise/fall time. The circuit may include a first input node configured to receive a first data signal and a second input node configured to receive a second data signal that is complementary of the first data signal. The circuit may also include a first stage having a first node coupled to the first input node and a second node coupled to the second input node and a second stage having a first node coupled to a third node of the first stage and a second node coupled to a fourth node of the first stage. The second stage may be configured to drive a load such as a laser. The circuit may further include a third input node configured to receive a third data signal and a fourth input node configured to receive a fourth data signal that is the complementary of the third data signal. Additionally, a control stage having a first node coupled the third input node, having a second node coupled to the fourth input node, having a third node coupled to the third node of the first stage and having a fourth node coupled to the fourth node of the first stage.
申请公布号
WO2008039781(A3)
申请公布日期
2008.07.03
申请号
WO2007US79430
申请日期
2007.09.25
申请人
FINISAR CORPORATION;NGUYEN, THE'LINH;MORAN, TIMOTHY, G.