| 摘要 |
<p>An output stage circuit includes an MOST (M) wherein a subthreshold current substantially flows between a drain and a source when the voltage of the gate is made equal to that of the source. In the output stage circuit, a voltage is applied to the gate of the MOST (M) to reversely bias between the gate and the source of the MOST (M) when the circuit is not activated. Namely, when the MOST (M) is of a p-channel, a higher voltage is applied to the gate compared with a p-type source, and when the MOST (M) is of an n-channel, a lower voltage is applied to the gate compared with an n-type source. When the circuit is activated, the reverse bias state is maintained or is controlled to be in a forward bias state, corresponding to the input voltage. The CMOS circuit, furthermore, a semiconductor device, which have a small leak current even with a low threshold voltage and operate at a high speed with a small voltage magnitude are provided.</p> |
