LOGIC CIRCUIT DESIGNING DEVICE FOR ASYNCHRONOUS LOGIC CIRCUIT, LOGIC CIRCUIT DESIGNING METHOD, AND LOGIC CIRCUIT DESIGNING PROGRAM

摘要

[PROBLEMS] A logic circuit designing circuit for an asynchronous logic circuit meeting the characteristic restriction of a state storage element represented by a latch or a flip-flop. [MEANS FOR SOLVING PROBLEMS] A state storage control signal transition sequence extracting section (112) extracts a signal transition sequence for generating a control signal pulse for a state storage element from a state transition graph inputted into a logic circuit designing device. A pulse generation path delay restriction setting adding section (115) sets a minimum delay restriction of a signal line path corresponding to the signal transition sequence as a minimum pulse width restriction value of the state storage element so as to perform logical synthesis.