| 摘要 |
A semiconductor memory device is provided to improve refresh characteristics of a DRAM by improving write operation characteristics. A bit line sense amplifier operating in response to one column decoder signal is arranged between bit line sense amplifiers transmitting data of a bit line to a data bus line(LIO) in response to another column decoder signal. A plurality of first sense amplifiers(20) amplify data of a corresponding bit line, and transmits the amplified data to a first data bus line in response to a first column decoder signal. A plurality of second sense amplifiers(20') amplify data of a corresponding bit line, and transmit the amplified data to a second data bus line in response to a second column decoder signal. The second sense amplifier is arranged among each first sense amplifier, and the first sense amplifier is arranged among each second sense amplifier.
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