| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To realize a memory test system which can improve throughput when testing a device under test. <P>SOLUTION: The memory test system comprises an ALPG 13 for generating a test pattern to test DUT section 17; a programmable logic circuit 16 including an FC section 14 for shaping a signal waveform to apply to the DUT section 17; a PE section 15 for transmitting the signal shaped by the FC section 14 to the DUT section 17 and receiving a response signal to the transmitted signal from the DUT section 17; a RAM 12 for storing total number M of tester pins and the number m2 of pins, when a signal is transmitted/received between PE section 15 and DUT section 17; and a control section 11 for reading the total number M of tester pins and the number m2 of the pins, calculating the number of testable DUT1 to DUTn of the DUT section 17, and setting the number of FC1 to FCn of the FC section 14 to the calculated number. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
