| 摘要 |
<p>Provided are a 2-transistor (2T) NOR cell array which includes at least a cell, and a cell comprising a selection transistor and a storage transistor including a charge storage floating gate or a charge storage dielectric, and a method of processing data of a 2T NOR flash memory cell which is used to store data in a 2T NOR cell array, read the stored data, and erase the stored data. The 2T NOR cell array includes a selection transistor and a storage transistor. The selection transistor includes a terminal connected to a bit line and a gate terminal applied with a selection signal. The storage transistor includes a terminal connected to the other terminal of the selection transistor, the other terminal connected to a common source line, and a gate applied with a control voltage. A back bias voltage is applied to bulk regions of the selection transistor and the storage transistor when a programming operation is performed, and a floating gate or a charge storage dielectric is provided between the gate and the bulk region of the storage transistor.</p> |
