SIMD PROCESSOR WITH REDUCTION UNIT

摘要

A single-instruction multiple-data processor (10) comprises a plurality of lanes (L₀-L₇). The number of lanes is at least three. The single-instruction multiple-data processor further comprises a computation unit (20) operatively connected to all of the plurality of lanes (L₀-L₇). The computation unit (20) is adapted to perform a computational operation involving data elements from all of the plurality of lanes (L₀-L₇) and generate a single output data element based on a result of said computational operation. The computation unit (20) is adapted to perform the computational operation as a comparison of the data elements from all of the plurality of lanes. A method of processing data in the single-instruction multiple-data processor (10) is also disclosed.