| 摘要 |
A clock buffer circuit and a semiconductor memory device including the same are provided to assure latch margin of an input signal by reducing a variable due to an internal clock pulse in the semiconductor memory device receiving an external signal synchronized with a rising and falling edge of an internal clock. According to a clock buffer circuit of a semiconductor memory device generating an internal clock for synchronizing an external signal, a rising clock buffer(200) generates a rising internal clock corresponding to the rising of an external clock by buffering the external clock. A falling clock buffer(220) generates a falling internal clock corresponding to the falling of the external clock by buffering the external clock. The external address is one of an address, a command and data. The rising clock buffer includes a non-inverting differential amplification part(202) outputting a clock in phase with the external clock by differentially amplifying the external clock and an inverted external clock, and a first delay part(204) outputting the rising internal clock by delaying an output clock of the non-inversion differential amplification part. The falling clock buffer includes an inversion differential amplification part(222) and a second delay part(224).
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