发明名称 Generation of Analog Voltage Using Self-Biased Capacitive Feedback Stage
摘要 Analog voltage drain with reduced current drain is achieved by a a new capacitive-divided feedback architecture. During the operational phase an op amp monitors a capacitively-divided fraction of the output voltage, and drives a current sink or source accordingly; during an initial phase the output is forced to the correct value by a different circuit, while the opamp is connected to self-tune itself in a way which removes DC offset effects.
申请公布号 US2008157731(A1) 申请公布日期 2008.07.03
申请号 US20070618917 申请日期 2007.01.01
申请人 SANDISK CORP. 发明人 PAN FENG
分类号 G05F1/10 主分类号 G05F1/10
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