METHOD FOR FORMING OF METAL WIRING IN SEMICONDUCTOR DIVICE

摘要

A method for manufacturing a metal line of a semiconductor device is provided to improve gap-fill of a copper plating layer within a via hole with an aspect ratio by performing an MCWE(Multi Cu Wet Etch) process. An interlayer dielectric(30) is formed on a semiconductor substrate(10) comprising lower wiring(20). A via hole is formed on the interlayer dielectric. A diffusion barrier layer(40) is formed on the interlayer dielectric. A copper plating layer is formed by forming a copper seed layer(50) and a copper layer(60) on the diffusion barrier layer and etching based on the copper plating layer filled within the via hole. The copper plating layer formation process is repeated until the via hole is filled up. Copper wiring is formed by flattening the via hole.