| 摘要 |
A column address enable signal generation circuit in a semiconductor memory device is provided to control pulse width of a column address enable signal in correspondence to pulse width of an inputted external clock. A clock period detection unit(210) detects period of an external clock in response to a pulse width information signal having pulse width corresponding to pulse width of the external clock. A column address enable signal generation unit(200) generates a column address enable signal enabled in response to a column access signal. A multiplexing unit(220) includes a number of delay devices to multiplex disable time of the column access signal in response to the detection signal outputted from the clock period detection unit.
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