A CMOS output buffer with ESD protection

摘要

The pullup and pulldown sections in each output buffer are fed from separate power rails 40,46;42,48;44,50 so that a positive ESD impulse on any I/O pad cannot couple through the pull-up circuit MP10 to the gate of the pull-down cascode device MNA and cause gate voltage induced current crowding (GVICC). The pulldown circuit in each block shares a common supply with the pullup circuit in adjacent blocks. Positive ESD impulses on the I/O pad may be discharged by parasitic lateral NPN transistors associated with the pull-down NMOS transistors (figure 2).