METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON

摘要

One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal Õ(0) to Õ(2 i -1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal Õ(0) to Õ(2 i -1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal Õ(0) to Õ(2 i -1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.