发明名称 Integrated circuit with integrated debugging mechanism for standard interface
摘要 A circuit having a corresponding method comprises one or more circuits each to produce one or more status signals, wherein each of the status signals represents a status of a respective one of the one or more circuits; a memory; a memory controller to store a plurality of samples of the one or more status signals in the memory; a plurality of input/output terminals; an interface in communication with one or more of the input/output terminals; and a debug circuit to transfer the one or more samples of the status signals from the memory to the interface.
申请公布号 US7395454(B1) 申请公布日期 2008.07.01
申请号 US20050028687 申请日期 2005.01.04
申请人 MARVELL ISRAEL (MISL) LTD. 发明人 WOHLGEMUTH ARON;GABAI AMIR;AVIVI AMIT
分类号 G06F11/00 主分类号 G06F11/00
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