发明名称 Method and relative circuit for incrementing, decrementing or two's complementing a bit string
摘要 A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least significant bit of the auxiliary string is independent from the bits of the first string, and any other bit of the auxiliary string. The method is particularly convenient for generating an overflow flag when the number to be output exceeds the representation interval. An overflow flag is generated by logically combining the most significant bits of the first and auxiliary strings.
申请公布号 US7395305(B2) 申请公布日期 2008.07.01
申请号 US20030651075 申请日期 2003.08.28
申请人 STMICROELECTRONICS S.R.L. 发明人 IACONO DANIELE LO
分类号 G06F7/50;G06F7/48;G06F7/505 主分类号 G06F7/50
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