POWER TRANSISTOR FEATURING A VARIABLE TOPOLOGY LAYOUT

摘要

A power transistor comprises a number of groups of gate fingers of various widths and can include uniform or non-uniform pitch. The widths may include any number of different widths. In one embodiment, there are included three widths W₁, W₂, and W₃, in which W₃>W₂>W₁. The groups of gate fingers are arranged from greater width to lesser width disposed from a periphery to a center of the device. In addition, the gate fingers are configured to have one of a centered justification, a gate pad side justification, and a drain pad side justification, along a dimension of the power transistor layout. In another embodiment, the groups of gate fingers having widths W₁, W₂, and W₃ are configured symmetrically about a center line of the device. The variable gate finger widths provide a level of greater power density at the outside of the die in relation to a power density at the center of the die. Asymmetrical arrangements of gate finger widths are also contemplated.