STRESS ENHANCED TRANSISTOR AND METHODS FOR ITS FABRICATION

摘要

A stress enhanced MOS transistor (30) and methods for its fabrication are provided. A semiconductor-on-insulator structure (36) is provided which includes a semiconductor layer (38) having a first surface (37). A strain- inducing epitaxial layer (50) is blanket deposited over the first surface (37), and can then be used to create a source region (51) and a drain region (52) which overlie the first surface (37).