| 摘要 |
A memory device and a semiconductor integrated circuit are provided to increase access efficiency by enabling a plurality of banks stored with access target data, in response to a first operation code, and to prevent degradation of effective bandwidth. A memory device includes a memory cell array including a plurality of word lines allocated to different row addresses, N banks(92) allocated to different bank addresses, and a row control part(87) controlling enabling of a word line in the bank in response to a first operation code. The row control part includes a multi bank enable control part and a row address calculation part. The multi bank enable control part generates a bank enable signal of M banks, according to a supplied bank address and multi bank information data supplied with the first operation code. The row address calculation part generates a row address of the M enabled banks, according to the supplied bank address and a supplied row address. The M enabled banks enable at least one word line according to the bank enable signal and a row address generated by the row address calculation part.
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