A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.
申请公布号
WO2008076892(A2)
申请公布日期
2008.06.26
申请号
WO2007US87592
申请日期
2007.12.14
申请人
MICROCHIP TECHNOLOGY INCORPORATED;TRIECE, JOSEPH, W.;PESAVENTO, RODNEY, J.;LAHTI, GREGG, D.;DAWSON, STEVEN
发明人
TRIECE, JOSEPH, W.;PESAVENTO, RODNEY, J.;LAHTI, GREGG, D.;DAWSON, STEVEN