发明名称 LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a multiplier with a logic reducing or excluding dependency of a programmable logic device (PLD) on a universal programmable resource by facilitating execution of multiplication larger than multiplication which can be executed in a single block in specialized processing blocks for the PLD. <P>SOLUTION: A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008146644(A) 申请公布日期 2008.06.26
申请号 JP20070311579 申请日期 2007.11.30
申请人 ALTERA CORP 发明人 LANGHAMMER MARTIN;THARMALINGAM KUMARA
分类号 G06F7/523;G06F7/00;H03K19/173 主分类号 G06F7/523
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