发明名称 Stacked-die packages with silicon vias and surface activated bonding
摘要 A system may include a first integrated circuit die including a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die including a second surface activated bonding site coupled to the first surface activated bonding site. A system may further include an integrated circuit package substrate coupled to the plurality of silicon vias, and a plurality of wirebonds coupled to the integrated circuit package substrate and to the first integrated circuit die.
申请公布号 US2008150155(A1) 申请公布日期 2008.06.26
申请号 US20060642293 申请日期 2006.12.20
申请人 PERIAMAN SHANGGAR;CHI OOI KOOI;ENG CHEAH BOK 发明人 PERIAMAN SHANGGAR;CHI OOI KOOI;ENG CHEAH BOK
分类号 H01L23/538;H01L21/60 主分类号 H01L23/538
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