A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.
申请公布号
WO2008026129(A3)
申请公布日期
2008.06.26
申请号
WO2007IB53344
申请日期
2007.08.22
申请人
KONINKLIJKE PHILIPS ELECTRONICS N. V.;SNOEIJ, MARTIJN, F.;MIEROP, ADRIANUS, J.;THEUWISSEN, ALBERT, J. P.;HUIJSING, JOHAN, H.
发明人
SNOEIJ, MARTIJN, F.;MIEROP, ADRIANUS, J.;THEUWISSEN, ALBERT, J. P.;HUIJSING, JOHAN, H.