发明名称 IMAGE PROCESSOR
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an image processor making an efficient access when practicing a data transfer. <P>SOLUTION: A writing address generating unit 11, based on writing macro block position information 204 inputted from outside, an address offset 205, and a frame size 206, stores the predetermined number of macro blocks of writing data 208 in a same row address in a bank of SDRAM 2, arranges macro blocks in such a manner that a macro block on an image space and a neighboring macro block including oblique directions are stored in the same row address of the same bank or in different banks of the SDRAM 2, and generates a writing address 207 consisting of a bank, a row address, and a column address of the SDRAM 2. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008146235(A) 申请公布日期 2008.06.26
申请号 JP20060330790 申请日期 2006.12.07
申请人 RENESAS TECHNOLOGY CORP 发明人 SATO HIDENORI;MINEGISHI TAKAYUKI
分类号 G06T1/60;G06F12/06;H04N19/00;H04N19/423;H04N19/503 主分类号 G06T1/60
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