发明名称 SETTING METHOD OF ERASURE VOLTAGE OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a setting method of an erasure voltage of a nonvolatile semiconductor memory device which enables simplification of high-speed negative voltage generation and a negative voltage generation charge pump by stepping down the voltage of deep well during erasure mode operation. <P>SOLUTION: When a negative voltage of a charge pump is input into a second well area 12-1 of a first conductivity type in which a path transistor 50-1 is formed and an end of a path transistor 15-1, and a predetermined voltage is applied to gates 17-1 to -4 of path transistor to output the negative voltage to a memory cell from another end 16-4 of the path transistor, potential of a first well areas 11-1 to -4 of a second conductivity type is stepped down to a predetermined level and a negative high voltage which is obtained by stepping down the potential of the second well areas 12-1 to -4 of the first conductivity type from the negative voltage of the charge pump to predetermined low potential, is output to a memory cell. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008146695(A) 申请公布日期 2008.06.26
申请号 JP20060329647 申请日期 2006.12.06
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 MURAKAMI HIROKI
分类号 G11C16/06 主分类号 G11C16/06
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