发明名称 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
摘要 A semiconductor device includes a double gate transistor which comprises an active region of a fin type and a pair of gate electrodes disposed opposite to each other through the active region. A height of the gate electrodes is higher than that of the active region and equal to or smaller than a calculated gate electrode height calculated using the following formula: <maths id="MATH-US-00001" num="00001"> <MATH OVERFLOW="SCROLL"> <MROW> <MROW> <MROW> <MO>(</MO> <MROW> <MROW> <MO>(</MO> <MROW> <MI>Gate</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MI>Electrode</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MROW> <MI>Height</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>[</MO> <MI>nm</MI> <MO>]</MO> </MROW> </MROW> <MO>)</MO> </MROW> <MO>-</MO> <MROW> <MO>(</MO> <MROW> <MI>Active</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MI>Region</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MROW> <MI>Height</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>[</MO> <MI>nm</MI> <MO>]</MO> </MROW> </MROW> <MO>)</MO> </MROW> </MROW> <MO>)</MO> </MROW> <MO>/</MO> <MROW> <MO>(</MO> <MROW> <MI>Active</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MI>Region</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MROW> <MI>Height</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>[</MO> <MI>nm</MI> <MO>]</MO> </MROW> </MROW> <MO>)</MO> </MROW> </MROW> <MO>=</MO> <MROW> <MROW> <MN>3.5</MN> <MO></MO> <MSTYLE> <mspace width="0.3em" height="0.3ex"/> </MSTYLE> <MO></MO> <MSUP> <MI></MI> <MROW> <MO>-</MO> <MN>5</MN> </MROW> </MSUP> <MO>x</MO> <MSUP> <MROW> <MO>(</MO> <MROW> <MI>Gate</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MROW> <MI>Length</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>[</MO> <MI>nm</MI> <MO>]</MO> </MROW> </MROW> <MO>)</MO> </MROW> <MN>2</MN> </MSUP> </MROW> <MO>-</MO> <MROW> <MN>0.002</MN> <MO>x</MO> <MROW> <MO>(</MO> <MROW> <MI>Gate</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO></MO> <MROW> <MI>Length</MI> <MO></MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>[</MO> <MI>nm</MI> <MO>]</MO> </MROW> </MROW> <MO>)</MO> </MROW> </MROW> <MO>+</MO> <MROW> <MN>0.16</MN> <MO>.</MO> </MROW> </MROW> </MROW> </MATH> </MATHS>
申请公布号 US2008150030(A1) 申请公布日期 2008.06.26
申请号 US20070959070 申请日期 2007.12.18
申请人 ELPIDA MEMORY, INC. 发明人 YOKOYAMA SHIGEYUKI;KOSUGE YU
分类号 H01L29/78;H01L21/336 主分类号 H01L29/78
代理机构 代理人
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