| 摘要 |
The component has processors (CPU A, CPU B) connected to program memories (ROM A, ROM B), electrically EPROMs (EEPROM A, EEPROM B) and RAMs (RAM A, RAM B), respectively. The processor (CPU B) is connected to the processor (CPU A) through a swap memory (DPR). The memory (EEPROM A) is only in read access for the processor (CPU A). The processor (CPU B) has a read-write access on the memory (EEPROM A). The processor (CPU A) has an interfacing bus that interfaces with the exterior of the component. |
