METHOD FOR FORMING VIA HOLE OF SEMICONDUCTOR DEVICE

摘要

A method for forming a via hole of a semiconductor device is provided to avoid polymer generated by etch of an interlayer dielectric for forming a via hole by forming a thin capping layer made of silicon nitride on the entire surface of a via hole structure and by selectively removing only the capping layer formed on the bottom of the via hole. An interlayer dielectric(25) is formed on a substrate(21) having a conductive unit(23) made of an arbitrary pattern. A part of the interlayer dielectric formed on the conductive unit is selectively removed to form a via hole(29) exposing the upper part of the conductive unit. A thin capping layer(27) is formed on the entire surface of the substrate having the via hole. The capping layer formed on the bottom surface of the via hole is selectively removed to complete the via hole. Silicon nitride can be deposited in a low temperature furnace to form the capping layer.